1. Field of the Invention
The present invention relates to a stacked semiconductor device having a package on package (PoP) structure in which multiple semiconductor packages are stacked in a multilayer form.
2. Description of the Related Art
As one form of a semiconductor package, a stacked semiconductor device having a PoP structure is known (see Japanese Patent Application Laid-Open No. 2011-14757). This is a structure in which a first semiconductor package as an upper semiconductor package and a second semiconductor package as a lower semiconductor package are stacked and the semiconductor packages are joined together by solder balls.
The first semiconductor package includes a first semiconductor element, and a first printed wiring board having the first semiconductor element mounted thereon. The first semiconductor element of the first semiconductor package is encapsulated in a resin. The second semiconductor package includes a second semiconductor element, and a second printed wiring board having the second semiconductor element mounted thereon. The first semiconductor element is a semiconductor chip such as a DDR memory. The second semiconductor element is a semiconductor chip such as a system LSI. The second semiconductor package is not encapsulated in a resin.
The printed wiring board of each semiconductor package has a solder resist formed thereon for covering a wiring pattern on a surface thereof. By providing openings having the same diameter in each solder resist, conductor lands formed on each printed wiring board are exposed. The lands on the printed wiring boards of the semiconductor packages are solder joined together by solder balls to form the stacked semiconductor device.
In the case of such a stacked semiconductor device, due to a difference in coefficient of linear expansion between the first semiconductor package and the second semiconductor package, warpage occurs in the stacked semiconductor device. This occurs due to a difference in coefficient of linear expansion among the encapsulation resin formed in the first semiconductor package and the first and second printed wiring boards.
Specifically, due to the difference in coefficient of linear expansion between the semiconductor packages, when the temperature changes in accordance with turning on/off the electronic apparatus, the second semiconductor package is deformed relatively in a horizontal direction and in a vertical direction with respect to the first semiconductor package. As a result, thermal stress concentrates on opening ends of a solder resist on the second printed wiring board at a solder joint portion to develop a crack at the solder joint portion.
In recent years, as the scale of the system becomes larger, more downsizing of the stacked semiconductor device is required. In order to meet the requirement, circuits are connected at a high density, fine wirings are used on the printed wiring boards, the diameters of vias for interlayer connection are reduced, and the printed wiring boards become thinner and thinner. Therefore, the problem of warpage of the stacked semiconductor device due to the change of the temperature in accordance with turning on/off of the electronic apparatus becomes more obvious.